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1. general description the 74HC573-Q100; 74hct573-q100 is a high -speed si-gate cmos device and is pin compatible with low-power schottky ttl (l sttl). it is specified in compliance with jedec standard no. 7a. the 74HC573-Q100; 74hct573-q100 has octal d-type transparent latches featuring separate d-type inputs for each latch and 3-state true outputs for bus-oriented applications. a latch enable (le) input and an output enable (oe ) input are common to all latches. when le is high, data at the dn inputs enter the latches. in this cond ition, the latches are transparent, i.e. a latch output changes state each time its corresponding d input changes. when le is low the latches store the information that was present at the d-inputs a set-up time preceding the high -to-low transition of le. when oe is low, the contents of the 8 latches are available at the outputs. when oe is high, the outputs go to the high-impedance off-state. operation of the oe input does not affect the state of the latches. this product has been qualified to the automotive electronics council (aec) standard q100 (grade 1) and is suitable for use in automotive applications. 2. features and benefits ? automotive product qualif ication in accordance with aec-q100 (grade 1) ? specified from ? 40 ? c to +85 ? c and from ? 40 ? c to +125 ? c ? input levels: ? for 74hc573: cmos level ? for 74hct573: ttl level ? inputs and outputs on opposite sides of package allowing easy interface with microprocessors ? useful as input or output port fo r microprocessors and microcomputers ? 3-state non-inverting outputs for bus-oriented applications ? common 3-state output enable input ? multiple package options ? esd protection: ? mil-std-883, method 3015 exceeds 2000 v ? hbm jesd22-a114f exceeds 2000 v ? mm jesd22-a115-a exceeds 200 v (c = 200 pf, r = 0 ? ) 74HC573-Q100; 74hct573-q100 octal d-type transparent latch; 3-state rev. 2 ? 16 august 2012 product data sheet
74hc_hct573_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 16 august 2012 2 of 19 nxp semiconductors 74HC573-Q100; 74hct573-q100 octal d-type transparent latch; 3-state 3. ordering information 4. functional diagram table 1. ordering information type number package temperature range name description version 74hc573d-q100 ? 40 ? c to +125 ? c so20 plastic small outline package; 20 leads; body width 7.5 mm sot163-1 74hct573d-q100 74hc573pw-q100 ? 40 ? c to +125 ? c tssop20 plastic thin shrink small outline package; 20 leads; body width 4.4 mm sot360-1 74hct573pw-q100 74hc573bq-q100 ? 40 ? c to +125 ? c dhvqfn20 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 20 terminals; body 2.5 ? 4.5 ? 0.85 mm sot764-1 74hct573bq-q100 fig 1. functional diagram mna809 3-state outputs latch 1 to 8 q0 q1 q2 q3 q4 q5 q6 q7 12 13 14 15 16 17 18 19 d0 d1 d2 d3 d4 d5 d6 d7 le oe 9 11 1 8 7 6 5 4 3 2
74hc_hct573_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 16 august 2012 3 of 19 nxp semiconductors 74HC573-Q100; 74hct573-q100 octal d-type transparent latch; 3-state fig 2. logic diagram 001aae075 q4 d4 dq q3 d3 dq q2 d2 dq q1 d1 d le q q0 d0 d latch 1 latch 2 latch 3 latch 4 latch 5 q le oe le le le le q5 d5 dq latch 6 le q6 d6 dq latch 7 le q7 d7 dq latch 8 le fig 3. logic symbol fig 4. iec logic symbol mna807 d0 d1 d2 d3 d4 d5 d6 d7 le oe q0 q1 q2 q3 q4 q5 q6 q7 1 11 12 13 14 15 16 17 18 19 9 8 7 6 5 4 3 2 mna808 12 13 14 15 16 17 18 11 c1 1 en1 1d 19 9 8 7 6 5 4 3 2
74hc_hct573_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 16 august 2012 4 of 19 nxp semiconductors 74HC573-Q100; 74hct573-q100 octal d-type transparent latch; 3-state 5. pinning information 5.1 pinning 5.2 pin description (1) the die substrate is attached to this pad using conductive die attach mate rial. it cannot be used as supply pin or input fig 5. pin configuration so20 and tssop20 fig 6. pin configuration dhvqfn20 aaa-003603 1 2 3 4 5 6 7 8 9 10 12 11 14 13 16 15 18 17 20 19 oe v cc d0 q0 d1 q1 d2 q2 d3 q3 d4 q4 d5 q5 d6 q6 d7 q7 gnd le 74HC573-Q100 74hct573-q100 aaa-003604 transparent top view q7 d6 d7 q6 d5 q5 d4 q4 d3 q3 d2 q2 d1 q1 d0 gnd(1) q0 gnd le oe v cc 9 12 8 13 7 14 6 15 5 16 4 17 3 18 2 19 10 11 1 20 terminal 1 index area 74HC573-Q100 74hct573-q100 table 2. pin description symbol pin description oe 1 3-state output enable input (active low) d[0:7] 2, 3, 4, 5, 6, 7, 8, 9 data input gnd 10 ground (0 v) le 11 latch enable input (active high) q[0:7] 19, 18, 17, 16, 15, 14, 13, 12 3-state latch output v cc 20 supply voltage
74hc_hct573_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 16 august 2012 5 of 19 nxp semiconductors 74HC573-Q100; 74hct573-q100 octal d-type transparent latch; 3-state 6. functional description [1] h = high voltage level; h = high voltage level one set-up time prior to the high-to-low le transition; l = low voltage level; l = low voltage level one set-up time prior to the high-to-low le transition; z = high-impedance off-state. 7. limiting values [1] for dip20 package: p tot derates linearly with 12 mw/k above 70 ? c. [2] for so20: p tot derates linearly with 8 mw/k above 70 ? c. for ssop20 and tssop20 packages: p tot derates linearly with 5.5 mw/k above 60 ? c. for dhvqfn20 package: p tot derates linearly with 4.5 mw/k above 60 ? c. table 3. function table [1] operating mode control input internal latches output oe le dn qn enable and read register (transparent mode) lhlll hhh latch and read register l l l l l hhh latch register and disable outputs h l l l z hhz table 4. limiting values in accordance with the absolute maximum rating system (iec 60134). voltages are referenced to gnd (ground = 0 v). symbol parameter conditions min max unit v cc supply voltage ? 0.5 +7 v i ik input clamping current v i < ? 0.5 v or v i >v cc +0.5 v - ? 20 ma i ok output clamping current v o < ? 0.5 v or v o >v cc +0.5v - ? 20 ma i o output current v o = ? 0.5 v to (v cc +0.5v) - ? 35 ma i cc supply current - +70 ma i gnd ground current - ? 70 ma t stg storage temperature ? 65 +150 ?c p tot total power dissipation dip20 package [1] - 750 mw so20, ssop20, tssop20 and dhvqfn20 packages [2] - 500 mw
74hc_hct573_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 16 august 2012 6 of 19 nxp semiconductors 74HC573-Q100; 74hct573-q100 octal d-type transparent latch; 3-state 8. recommended operating conditions 9. static characteristics table 5. recommended operating conditions voltages are referenced to gnd (ground = 0 v) symbol parameter conditions 74HC573-Q100 74hct573-q100 unit min typ max min typ max v cc supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 v v i input voltage 0 - v cc 0- v cc v v o output voltage 0 - v cc 0- v cc v t amb ambient temperature ? 40 +25 +125 ? 40 +25 +125 ?c ? t/ ? v input transition rise and fall rate v cc = 2.0 v - - 625 - - - ns/v v cc = 4.5 v - 1.67 139 - 1.67 139 ns/v v cc = 6.0 v--83---ns/v table 6. static characteristics at recommended operating conditions; volt ages are referenced to gnd (ground = 0 v). symbol parameter conditions 25 ?c ? 40 ? c to +85 ?c ? 40 ? c to +125 ?c unit min typ max min max min max 74HC573-Q100 v ih high-level input voltage v cc = 2.0 v 1.5 1.2 - 1.5 - 1.5 - v v cc = 4.5 v 3.15 2.4 - 3.15 - 3.15 - v v cc = 6.0 v 4.2 3.2 - 4.2 - 4.2 - v v il low-level input voltage v cc = 2.0 v - 0.8 0.5 - 0.5 - 0.5 v v cc = 4.5 v - 2.1 1.35 - 1.35 - 1.35 v v cc = 6.0 v - 2.8 1.8 - 1.8 - 1.8 v v oh high-level output voltage v i =v ih or v il i o = ? 20 ? a; v cc = 2.0 v 1.9 2.0 - 1.9 - 1.9 - v i o = ? 20 ? a; v cc = 4.5 v 4.4 4.5 - 4.4 - 4.4 - v i o = ? 20 ? a; v cc = 6.0 v 5.9 6.0 - 5.9 - 5.9 - v i o = ? 6.0 ma; v cc = 4.5 v 3.98 4.32 - 3.84 - 3.7 - v i o = ? 7.8 ma; v cc = 6.0 v 5.48 5.81 - 5.34 - 5.2 - v v ol low-level output voltage v i =v ih or v il i o =20 ? a; v cc = 2.0 v - 0 0.1 - 0.1 - 0.1 v i o =20 ? a; v cc = 4.5 v - 0 0.1 - 0.1 - 0.1 v i o =20 ? a; v cc = 6.0 v - 0 0.1 - 0.1 - 0.1 v i o = 6.0 ma; v cc = 4.5 v - 0.15 0.26 - 0.33 - 0.4 v i o = 7.8 ma; v cc = 6.0 v - 0.16 0.26 - 0.33 - 0.4 v i i input leakage current v i =v cc or gnd; v cc =6.0v -- ? 0.1 - ? 1.0 - ? 1.0 ? a i oz off-state output current v i =v ih or v il ; v o =v cc or gnd; v cc =6.0v -- ? 0.5 - ? 5.0 - ? 10.0 ? a
74hc_hct573_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 16 august 2012 7 of 19 nxp semiconductors 74HC573-Q100; 74hct573-q100 octal d-type transparent latch; 3-state i cc supply current v i =v cc or gnd; i o =0a; v cc =6.0v - - 8.0 - 80 - 160 ? a c i input capacitance -3.5- pf 74hct573-q100 v ih high-level input voltage v cc = 4.5 v to 5.5 v 2.0 1.6 - 2.0 - 2.0 - v v il low-level input voltage v cc = 4.5 v to 5.5 v - 1.2 0.8 - 0.8 - 0.8 v v oh high-level output voltage v i =v ih or v il ; v cc =4.5v i o = ? 20 ? a 4.4 4.5 - 4.4 - 4.4 - v i o = ? 6 ma 3.98 4.32 - 3.84 - 3.7 - v v ol low-level output voltage v i =v ih or v il ; v cc =4.5v i o =20 ? a - 0 0.1 - 0.1 - 0.1 v i o = 6.0 ma - 0.16 0.26 - 0.33 - 0.4 v i i input leakage current v i =v cc or gnd; v cc =5.5v -- ? 0.1 - ? 1.0 - ? 1.0 ? a i oz off-state output current v i =v ih or v il ; v cc =5.5v; v o =v cc or gnd per input pin; other inputs at v cc or gnd; i o =0a -- ? 0.5 - ? 5.0 - ? 10 ? a i cc supply current v i =v cc or gnd; i o =0a; v cc =5.5v - - 8.0 - 80 - 160 ? a ? i cc additional supply current v i =v cc ? 2.1 v; other inputs at v cc or gnd; v cc = 4.5 v to 5.5 v; i o =0a per input pin; dn inputs - 35 126 - 158 - 172 ? a per input pin; le input - 65 234 - 293 - 319 ? a per input pin; oe input - 125 450 - 563 - 613 ? a c i input capacitance -3.5- pf table 6. static characteristics ?continued at recommended operating conditions; volt ages are referenced to gnd (ground = 0 v). symbol parameter conditions 25 ?c ? 40 ? c to +85 ?c ? 40 ? c to +125 ?c unit min typ max min max min max
74hc_hct573_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 16 august 2012 8 of 19 nxp semiconductors 74HC573-Q100; 74hct573-q100 octal d-type transparent latch; 3-state 10. dynamic characteristics table 7. dynamic characteristics voltages are referenced to gnd (ground = 0 v); c l = 50 pf unless otherwise specified; for test circuit see figure 11 . symbol parameter conditions 25 ?c ? 40 ? c to +85 ?c ? 40 ? c to +125 ? c unit min typ max min max min max for type 74HC573-Q100 t pd propagation delay dn to qn; see figure 7 [1] v cc = 2.0 v - 47 150 - 190 - 225 ns v cc = 4.5 v - 17 30 - 38 - 45 ns v cc =5v; c l =15pf - 14 - - - - - ns v cc = 6.0 v - 14 26 - 33 - 38 ns t pd propagation delay le to qn; see figure 8 [1] v cc = 2.0 v - 50 150 - 190 - 225 ns v cc = 4.5 v - 18 30 - 38 - 45 ns v cc =5v; c l =15pf - 15 - - - - - ns v cc = 6.0 v - 14 26 - 33 - 38 ns t en enable time oe to qn; see figure 9 [2] v cc = 2.0 v - 44 140 - 175 - 210 ns v cc = 4.5 v - 16 28 - 35 - 42 ns v cc = 6.0 v - 13 24 - 30 - 36 ns t dis disable time oe to qn; see figure 9 [3] v cc = 2.0 v - 55 150 - 190 - 225 ns v cc = 4.5 v - 20 30 - 38 - 45 ns v cc = 6.0 v - 16 26 - 33 - 38 ns t t transition time qn; see figure 7 [4] v cc = 2.0 v - 14 60 - 75 - 90 ns v cc = 4.5 v - 5 12 - 15 - 18 ns v cc = 6.0 v - 4 10 - 13 - 15 ns t w pulse width le high; see figure 8 v cc = 2.0 v 80 14 - 100 - 120 - ns v cc = 4.5 v 16 5 - 20 - 24 - ns v cc = 6.0 v 14 4 - 17 - 20 - ns t su set-up time dn to le; see figure 10 v cc = 2.0 v 50 11 - 65 - 75 - ns v cc = 4.5 v 10 4 - 13 - 15 - ns v cc = 6.0 v 9 3 - 11 - 13 - ns t h hold time dn to le; see figure 10 v cc = 2.0 v 5 3 - 5 - 5 - ns v cc = 4.5 v 5 1 - 5 - 5 - ns v cc = 6.0 v 5 1 - 5 - 5 - ns c pd power dissipation capacitance c l =50pf;f=1 mhz; v i =gndtov cc [5] -26- - - - -pf
74hc_hct573_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 16 august 2012 9 of 19 nxp semiconductors 74HC573-Q100; 74hct573-q100 octal d-type transparent latch; 3-state [1] t pd is the same as t plh and t phl . [2] t en is the same as t pzh and t pzl . [3] t dis is the same as t plz and t phz . [4] t t is the same as t thl and t tlh . [5] c pd is used to determine the dynamic power dissipation (p d in ? w). p d =c pd ? v cc 2 ? f i ? n+ ? (c l ? v cc 2 ? f o ) where: f i = input frequency in mhz; f o = output frequency in mhz; c l = output load capacitance in pf; v cc = supply voltage in v; n = number of inputs switching; ? (c l ? v cc 2 ? f o ) = sum of outputs. for type 74hct573-q100 t pd propagation delay dn to qn; see figure 7 [1] v cc = 4.5 v - 20 35 - 44 - 53 ns v cc =5v; c l =15pf - 17 - - - - - ns t pd propagation delay le to qn; see figure 8 [1] v cc = 4.5 v - 18 35 - 44 - 53 ns v cc =5v; c l =15pf - 15 - - - - - ns t en enable time oe to qn; see figure 9 [2] v cc = 4.5 v - 17 30 - 38 - 45 ns t dis disable time oe to qn; see figure 9 [3] v cc = 4.5 v - 18 30 - 38 - 45 ns t t transition time qn; see figure 7 [4] v cc = 4.5 v - 5 12 - 15 - 18 ns t w pulse width le high; see figure 8 v cc = 4.5 v 16 5 - 20 - 24 - ns t su set-up time dn to le; see figure 10 v cc = 4.5 v 13 7 - 16 - 20 - ns t h hold time dn to le; see figure 10 v cc = 4.5 v 9 4 - 11 - 15 - ns c pd power dissipation capacitance c l =50pf;f=1 mhz; v i =gndtov cc [5] -26- - - - -pf table 7. dynamic characteristics ?continued voltages are referenced to gnd (ground = 0 v); c l = 50 pf unless otherwise specified; for test circuit see figure 11 . symbol parameter conditions 25 ?c ? 40 ? c to +85 ?c ? 40 ? c to +125 ? c unit min typ max min max min max
74hc_hct573_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 16 august 2012 10 of 19 nxp semiconductors 74HC573-Q100; 74hct573-q100 octal d-type transparent latch; 3-state 11. waveforms measurement points are given in table 8 . fig 7. propagation delay data input (dn) to output (qn) and output transition time 001aae082 dn input qn output v m t plh t phl t thl t tlh v m 90 % 10 % measurement points are given in table 8 . fig 8. pulse width latch enable input (le), propagation delay latch enable input (le) to output (qn) and output transition time v m v m t plh t phl t w le input qn output 001aae083 t tlh t thl 90 % 10 %
74hc_hct573_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 16 august 2012 11 of 19 nxp semiconductors 74HC573-Q100; 74hct573-q100 octal d-type transparent latch; 3-state measurement points are given in table 8 . v ol and v oh are typical voltage output levels that occur with the output load. fig 9. enable and disable times 001aae307 t plz t phz outputs disabled outputs enabled 90% 10% outputs enabled output low-to-off off-to-low output high-to-off off-to-high oe input v i v ol v oh v cc v m gnd gnd t pzl t pzh v m v m measurement points are given in table 8 . the shaded areas indicate when the input is per mitted to change for predictable output performance. fig 10. set-up and hold times for da ta input (dn) to latch input (le) 001aae084 v m le input dn input v m t h t su t h t su table 8. measurement points type input output v m v m 74HC573-Q100 0.5v cc 0.5v cc 74hct573-q100 1.3 v 1.3 v
74hc_hct573_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 16 august 2012 12 of 19 nxp semiconductors 74HC573-Q100; 74hct573-q100 octal d-type transparent latch; 3-state test data is given in table 9 . definitions test circuit: r t = termination resistance should be equal to output impedance z o of the pulse generator. c l = load capacitance including jig and probe capacitance. r l = load resistance. s1 = test selection switch. fig 11. test circuit for measuring switching times v m v m t w t w 10 % 90 % 0 v v i v i negative pulse positive pulse 0 v v m v m 90 % 10 % t f t r t r t f 001aad983 dut v cc v cc v i v o r t r l s1 c l open g table 9. test data type input load s1 position v i t r , t f c l r l t phl , t plh t pzh , t phz t pzl , t plz 74HC573-Q100 v cc 6ns 15pf, 50 pf 1k ? open gnd v cc 74hct573-q100 3 v 6 ns 15 pf, 50 pf 1 k ? open gnd v cc
74hc_hct573_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 16 august 2012 13 of 19 nxp semiconductors 74HC573-Q100; 74hct573-q100 octal d-type transparent latch; 3-state 12. package outline fig 12. package outline sot163-1 (so20) unit a max. a 1 a 2 a 3 b p cd (1) e (1) (1) eh e ll p q z ywv references outline version european projection issue date iec jedec jeita mm inches 2.65 0.3 0.1 2.45 2.25 0.49 0.36 0.32 0.23 13.0 12.6 7.6 7.4 1.27 10.65 10.00 1.1 1.0 0.9 0.4 8 0 o o 0.25 0.1 dimensions (inch dimensions are derived from the original mm dimensions) note 1. plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 1.1 0.4 sot163-1 10 20 w m b p detail x z e 11 1 d y 0.25 075e04 ms-013 pin 1 index 0.1 0.012 0.004 0.096 0.089 0.019 0.014 0.013 0.009 0.51 0.49 0.30 0.29 0.05 1.4 0.055 0.419 0.394 0.043 0.039 0.035 0.016 0.01 0.25 0.01 0.004 0.043 0.016 0.01 0 5 10 mm scale x a a 1 a 2 h e l p q e c l v m a (a ) 3 a so20: plastic small outline package; 20 leads; body width 7.5 mm sot163-1 99-12-27 03-02-19
74hc_hct573_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 16 august 2012 14 of 19 nxp semiconductors 74HC573-Q100; 74hct573-q100 octal d-type transparent latch; 3-state fig 13. package outline sot360-1 (tssop20) unit a 1 a 2 a 3 b p cd (1) e (2) (1) eh e ll p qz ywv references outline version european projection issue date iec jedec jeita mm 0.15 0.05 0.95 0.80 0.30 0.19 0.2 0.1 6.6 6.4 4.5 4.3 0.65 6.6 6.2 0.4 0.3 0.5 0.2 8 0 o o 0.13 0.1 0.2 1 dimensions (mm are the original dimensions) notes 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. plastic interlead protrusions of 0.25 mm maximum per side are not included. 0.75 0.50 sot360-1 mo-153 99-12-27 03-02-19 w m b p d z e 0.25 11 0 20 11 pin 1 index a a 1 a 2 l p q detail x l (a ) 3 h e e c v m a x a y 0 2.5 5 mm scale tssop20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm sot360-1 a max. 1.1
74hc_hct573_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 16 august 2012 15 of 19 nxp semiconductors 74HC573-Q100; 74hct573-q100 octal d-type transparent latch; 3-state fig 14. package outline sot764-1 (dhvqfn20) terminal 1 index area 0.5 1 a 1 e h b unit y e 0.2 c references outline version european projection issue date iec jedec jeita mm 4.6 4.4 d h 3.15 2.85 y 1 2.6 2.4 1.15 0.85 e 1 3.5 0.30 0.18 0.05 0.00 0.05 0.1 dimensions (mm are the original dimensions) sot764-1 mo-241 - - - - - - 0.5 0.3 l 0.1 v 0.05 w 0 2.5 5 mm scale sot764-1 dhvqfn20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 20 terminals; body 2.5 x 4.5 x 0.85 mm a (1) max. a a 1 c detail x y y 1 c e l e h d h e e 1 b 29 19 12 11 10 1 20 x d e c b a terminal 1 index area ac c b v m w m e (1) note 1. plastic or metal protrusions of 0.075 mm maximum per side are not included. d (1) 02-10-17 03-01-27
74hc_hct573_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 16 august 2012 16 of 19 nxp semiconductors 74HC573-Q100; 74hct573-q100 octal d-type transparent latch; 3-state 13. abbreviations 14. revision history table 10. abbreviations acronym description cmos complementary metal oxide semiconductor esd electrostatic discharge hbm human body model mm machine model ttl transistor-transistor logic mil military table 11. revision history document id release date data sheet status change notice supersedes 74hc_hct573_q100 v.2 20120816 product data sheet - 74hc_hct573_q100 v.1 modifications: ? alternative descriptive title corrected (errata). 74hc_hct573_q100 v.1 20120802 product data sheet - -
74hc_hct573_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 16 august 2012 17 of 19 nxp semiconductors 74HC573-Q100; 74hct573-q100 octal d-type transparent latch; 3-state 15. legal information 15.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 15.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 15.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such info rmation. nxp semiconductors takes no responsibility for the content in this document if provided by an information source outside of nxp semiconductors. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the terms and conditions of commercial sale of nxp semiconductors. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use in automotive applications ? this nxp semiconductors product has been qualified for use in automotive applications. unless otherwise agreed in writing, the product is not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors and its suppliers accept no liability for inclusion and/or use of nxp semiconducto rs products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers are responsible for the design and operation of their applications and products using nxp semiconductors products, and nxp semiconductors accepts no liability for any assistance with applications or customer product design. it is customer?s sole responsibility to determine whether the nxp semiconductors product is suitable and fit for the customer?s applications and products planned, as well as fo r the planned application and use of customer?s third party customer(s). customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer?s applications or products, or the application or use by customer?s third party customer(s). customer is responsible for doing all necessary testing for the customer?s applic ations and products using nxp semiconductors products in order to av oid a default of the applications and the products or of the application or use by customer?s third party customer(s). nxp does not accept any liability in this respect. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this document contains the product specification.
74hc_hct573_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 16 august 2012 18 of 19 nxp semiconductors 74HC573-Q100; 74hct573-q100 octal d-type transparent latch; 3-state no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any licens e under any copyrights, patents or other industrial or intellectual property rights. export control ? this document as well as the item(s) described herein may be subject to export control regu lations. export might require a prior authorization from competent authorities. translations ? a non-english (translated) version of a document is for reference only. the english version shall prevail in case of any discrepancy between the translated and english versions. 15.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. 16. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com
nxp semiconductors 74HC573-Q100; 74hct573-q100 octal d-type transparent latch; 3-state ? nxp b.v. 2012. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 16 august 2012 document identifier: 74hc_hct573_q100 please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 17. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 pinning information . . . . . . . . . . . . . . . . . . . . . . 4 5.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 functional description . . . . . . . . . . . . . . . . . . . 5 7 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 8 recommended operating conditions. . . . . . . . 6 9 static characteristics. . . . . . . . . . . . . . . . . . . . . 6 10 dynamic characteristics . . . . . . . . . . . . . . . . . . 8 11 waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 12 package outline . . . . . . . . . . . . . . . . . . . . . . . . 13 13 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 16 14 revision history . . . . . . . . . . . . . . . . . . . . . . . . 16 15 legal information. . . . . . . . . . . . . . . . . . . . . . . 17 15.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 17 15.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 15.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 15.4 trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 18 16 contact information. . . . . . . . . . . . . . . . . . . . . 18 17 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

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